Semiconductors

Caspia Technologies Unveils A Breakthrough in RTL Security Verification Paving the Way for Agentic Silicon Security

• In a significant advancement for the semiconductor industry, Caspia Technologies announced the broad availability of CODAx V2026 • 1, its flagship RTL security analyzer • The new

Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic Engineering

• At the 2026 Chiplet Summit, Synopsys presented a bold vision for the future of semiconductor innovation: AI-driven multi-die design powered by agentic intelligence • As the semic

An Agentic Formal Verifier. Innovation in Verification

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40 PCB Design Tips Every Designer Should Know: eBook

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Back-End Automation Tackles Growing Complexity

• As packaging complexity rises, the industry faces gaps in data, inspection, and process integration. • Experts at the table: Semiconductor Engineering sat down to discuss back-en

What Designers Need to Know About UALink for Scalable AI Systems

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Blog Review: Feb. 25

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Purpose-Built Tools for Connected Design

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Survey of DL-Based LiDAR Super-Resolution For Autonomous Driving (University College London)

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Reimagining Compute in the Age of Dispersed Intelligence

• At the 2025 RISC-V Summit, amid debates over cloud scaling and AI cost, DeepComputing CEO Yuning Liang offered a radical view: the future of intelligence isn’t in the cloud at al

Three New ALD/MLD Processes for Co-organic Thin Films (Aalto University, RUB et al.)

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Siemens to Deliver Industry-Leading PCB Test Engineering Solutions

• Siemens has strengthened its position in EDA and manufacturing by acquiring ASTER Technologies, a specialist in test and reliability solutions for printed circuit boards. • The a

Agentic EDA Panel Review Suggests Promise and Near-Term Guidance

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Intel, SambaNova Planning Multi-Year Collaboration for Xeon-Based AI Inference

• As AI workloads become more diverse and complex, organizations are looking for different solutions for different needs. • This is driving demand for more heterogeneous infrastruc

Chip Industry Technical Paper Roundup: Feb. 24

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Research Bits: Feb. 24

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Chiplets 2026: Where Are We Today?

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Ultrafast Laser Filamentation Dictates Energy Deposition in Narrow-Gap Semiconductors

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ReRAM-based Neo-Hebbian Synapses For Training Neuromorphic HW (IIT Madras, UCSB)

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Cadence Unwraps Agentic AI Super Agent for Chip Design and Verification

• Cadence introduces ChipStack AI Super Agent, an agentic AI platform automating front‑end silicon design. • The Super Agent streamlines design and verification, reducing manual ef

3D Atomic-Scale Metrology of Strain Relaxation And Roughness in GAAFETs Via Electron Ptychography (Cornell, ASM, TSMC)

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Hardware is the Center of the Universe (Again)

• The 40-Year Evolution of Hardware-Assisted Verification - From In-Circuit Emulation to AI-Era Full-Stack Validation For more than a decade, Hardware-Assisted Verification platfor

Smarter ECOs: Inside Easy-Logic's ASIC Optimization Engine

• Easy-Logic Technology Ltd.is a specialized Electronic Design Automation (EDA) company focused on solving one of the most complex and time-sensitive challenges in semiconductor de

The Name Changes but the Vision Remains the Same - ESD Alliance Through the Years

• The Electronic System Design Alliance (ESDA) has been at the center of the EDA industry through its many changes over the years. • It occurred to me that an update on this organi

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

• Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs. • Key Takeaways Backside power delivery networks delive

New Performance Requirements For Audio

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Survey of GenAI Across the Full Computing Stack, From SW To Silicon (Harvard)

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TSMC Process Simplification for Advanced Nodes

• In the modern world, the semiconductor industry stands at the heart of technological innovation. • From smartphones and laptops to advanced medical devices and artificial intelli

Accelerator Architecture: Fusion-Aware Mapper (MIT)

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Survey of GenAI Across the Full Computing Stack, From SW To Silicon (Harvard)

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CEO Interview with Juniyali Nauriyal of Photonect

• Juniyali Nauriyal is the CEO and Co-Founder of Photonect, a photonics startup focused on commercializing advanced fiber-to-chip attachment technologies. • Juniyali is the co-inve

Electrical Model of the Bitflip in SRAM Under Laser Illumination Simulating Laser Fault Injection

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Nanoscale MoS₂-based Memristors Integrated into CMOS Microchips

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What is the 3nm Pessimism Wall and Why is it An Economic Crisis?

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Discipline Will Keep Memory Market Tight

• Post‑AI market shift may constrain DRAM supply. • Manufacturers anticipate tighter inventory and pricing pressures. • Demand for high‑performance memory remains strong. • Supply

CEO Interview with Aftkhar Aslam of yieldWerx

• Aftkhar Aslam is the Co-Founder and Chief Executive Officer of yieldWerx and a semiconductor industry veteran with more than 30 years of experience spanning manufacturing, test e

Chip Industry Week in Review

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The On-Device LLM Revolution

• Why 3B to 30B models are moving to the edge - and what that means for silicon. • The AI world is experiencing a fundamental shift. • After years of cloud-centric inference domina

Intelligent Networks: Power, Reliability, and Maintenance in Telecom - Webinar Preview

• The upcoming webinar ‘Intelligent Networks: Power, Reliability, and Maintenance in Telecom’ will focus on how telecommunications networks are adapting to growing demands for effi

Custom IC Design using Additive Learning

• Custom IC design has demanding technical requirements to produce accurate simulation results for timing and power analysis in the shortest run times. • EDA vendors have been rush

LUBIS EDA: Addressing the Verification Bottleneck in Modern Chip Design

• LUBIS EDA is a Germany-based EDA company that specializes in formal verification, a mathematically rigorous method for proving that a chip design behaves correctly under all poss

Redefining Backside Metallization: Low‑Temperature Solutions For HDFO And S‑SWIFT Designs

• Efficient heat dissipation is critical in fan-out packages. • As chip performance and integration continue to advance, thermal dissipation control has become increasingly critica

Understanding Within-Wafer Variations: A Virtual Fabrication Approach

• Within-wafer variations cause performance differences across dies on a single wafer. • A virtual fabrication approach models these variations without physical wafer testing. • Se

Force Fields Will Accelerate Atomistic Simulations By 10,000× In 2026, Unlocking New Era Of Discovery

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Laser Arrays May Simplify Co-Packaged Optics

• Monolithic tunable lasers can adapt statically and dynamically. • Key Takeaways The move to co-packaged optics (CPO) holds the promise of putting photonic ICs (PICs) and electron

Leading At Light Speed: What Makes Photonics Leadership Different

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SEMI 2026 U.S. Policy Strategy

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Why Indium Oxide Chips Are Getting So Much Attention

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When Cleaning Chips Isn't Clean Enough

• Contamination is a systems-level limiter at advanced nodes, and there’s no simple solution to fix it. • Key Takeaways For much of the semiconductor industry’s history, contaminat

Enabling the Industry's First GPU-Accelerated Manufacturing Platform

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Intel Corporation to Participate in Upcoming Investor Conference

• Intel CFO will participate in a fireside chat at the Morgan Stanley Conference. • SANTA CLARA, Calif., Feb. • 18, 2025 - Intel Corporation today announced that David Zinsner, exe

New Class Of Semiconductors Made Of Germanium-Tin Alloy (University of Edinburgh et al.)

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Data Centers, Semiconductors, And Sovereignty: The Upcoming AI Divide

• What Is The AI Divide In Data Centers, Semiconductors, And Sovereignty? • TheAI dividerepresents a strategic inflection point for global business. • Those without these resources

AI + Mobile Networks: Intel Showcases What's Next at MWC 2026

• See how Intel’s proven 5G ecosystem delivers live-network AI inference on a single, open platform - maximizing infrastructure ROI today and paving a seamless path to 6G SANTA CLA

Cadence Unveils AI Agent to Accelerate Chip Design

• Cadence launches ChipStack AI Super Agent, first agentic workflow for silicon design and verification. • Claims up to 10× productivity gains, accelerating front‑end chip developm

Intel Launches new Intel® Xeon® 600 Processors for Workstation

• Up to 86 performance cores deliver unprecedented multi-threaded speed for demanding professional workloads. • 128 lanes of PCIe 5.0 connectivity enable ultra-fast data transfer f

Intel to Match Federal Contributions Under Trump Accounts Program for Employees' Families

• Intel matches $1,000 federal contribution for eligible children in 530A Trump Accounts. • Program supports U.S. employees’ families, providing tax‑deferred savings for kids under

Intel Reports Fourth-Quarter and Full-Year 2025 Financial Results

• Intel releases Q4 2025 earnings news and presentation on Investor Relations site. • Earnings call starts at 2 p.m. PDT; webcast available at www.intc.com . • CFO Dave Zinsner and

Postcard from CES 2026: Intel Launches Series 3 CPUs With 200+ Laptop Designs Coming

• Looking for a new Series 3 laptop? • You’ve come to the right place. • Earlier this week at CES 2026 in Las Vegas, Intel launched theIntel® Core™Ultra Series 3processors. • The l

Intel to Report Fourth-Quarter and Full-Year 2025 Financial Results

• Intel will deliver its report after market close on January 22. • SANTA CLARA, Calif., Jan. • 7, 2026 - Intel Corporation today announced that it will report fourth-quarter and f