• Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs. • Key Takeaways Backside power delivery networks deliver power directly to leading-edge transistors from below the wafer, an architectural change that speeds processor performance, slashes power losses, and boosts power efficiency. • But a BPDN also calls for many new manufacturing strategies to remove most of the silicon wafer, precisely align nanoTSVs with transistor source/drains, and new modeling efforts to reduce the thermal penalty associated with confining hot transistors between the frontside and backside interconnect stacks. • Still, leading IC manufacturers are making significant progress, especially given the near-simultaneous transition to nanosheet FETs from finFETs. • Intel recently moved its 18A process with RibbonFET transistors and PowerVia into production. • Samsung, an early leader that adopted gate-all-around (GAA) transistors at its 3nm node in 2022, plans to introduce backside power at its 2nm node (SF2).

Article Summaries:

  • Backside power delivery networks (BPDN) move the power grid to the wafer’s rear, reducing front‑side congestion and cutting voltage drop by up to 30%. This architectural shift improves power integrity, lowers lithography costs, and frees front‑side metal for signal routing, boosting cell density by 5‑10 %. Major foundries are advancing the technology: Intel’s 18A process now uses RibbonFETs and PowerVia; Samsung plans backside power for its 2 nm GAA node (SF2); TSMC will introduce GAA at 2 nm (N2) and a Super Power Rail at 1.6 nm (A16). Challenges remain in wafer removal, TSV alignment, and thermal modeling, but progress is rapid.
  • Backside power delivery networks (BPDN) relocate the power grid to the wafer’s underside, freeing front‑side metal for signals and cutting voltage drop by up to 30 %. The change improves power integrity, reduces lithography costs, and complements gate‑all‑around (GAA) devices by providing a more direct, low‑resistance path to transistor sources. However, fabs must adopt new manufacturing steps-removing most of the wafer, aligning nano‑TSVs with transistor contacts, and modeling thermal penalties from confining hot transistors between front‑ and back‑side interconnects. Leading foundries are advancing the technology: Intel’s 18A process uses RibbonFETs and PowerVia, Samsung plans backside power at its 2 nm node, and TSMC will introduce GAA at 2 nm and a Super Power Rail at 16 Å.

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