• Home Systems & Design Low Power - High Performance Manufacturing, Packaging & Materials Test, Measurement & Analytics Auto, Security & Enabling Technologies Special Reports Business & Startups Jobs Knowledge Center Technical PapersHome’;AI/ML/DLArchitecturesAutomotive/ AerospaceCommunication/Data MovementDesign & VerificationLithographyManufacturingMaterialsMemoryOptoelectronics / PhotonicsPackagingPower & PerformanceQuantumSecurityTest, Measurement, Analytics tech papersTransistorsZ-End Applications Home AI/ML/DL Architectures Automotive/ Aerospace Communication/Data Movement Design & Verification Lithography Manufacturing Materials Memory Optoelectronics / Photonics Packaging Power & Performance Quantum Security Test, Measurement, Analytics tech papers Transistors Z-End Applications Events & WebinarsEventsWebinars Events Webinars Videos & ResearchVideosIndustry Research Videos Industry Research Newsletters & StoreNewslettersStore Newsletters Store MENUHomeSpecial ReportsSystems & DesignLow Power-High PerformanceManufacturing, Packaging & MaterialsTest, Measurement & AnalyticsAuto, Security & Enabling TechnologiesKnowledge CenterVideosStartup CornerBusiness & StartupsJobsTechnical PapersEventsWebinarsIndustry ResearchNewslettersStoreSpecial Reports Home Special Reports Systems & Design Low Power-High Performance Manufacturing, Packaging & Materials Test, Measurement & Analytics Auto, Security & Enabling Technologies Knowledge Center Videos Startup Corner Business & Startups Jobs Technical Papers Events Webinars Industry Research Newsletters Store Special Reports Accelerator Architecture: Fusion-Aware Mapper (MIT) Researchers fromMITpublished “Fast and Fusiest: An Optimal Fusion-Aware Mapper for Accelerator Modeling and Evaluation.” Abstract “The latency and energy of tensor algebra accelerators depend on how data movement and operations are scheduled (i.e., mapped) onto accelerators, so determining the potential of an accelerator architecture requires both a perfor

Article Summaries:

  • MIT researchers have introduced the Fast and Fusiest Mapper (FFM), a new tool that rapidly identifies optimal data‑mapping strategies for tensor‑algebra accelerators. FFM tackles the exponential growth of fused mappings-where data is kept on‑chip between computation steps-by pruning partial mappings that can never belong to an optimal solution. It then stitches remaining partial mappings to construct full, energy‑efficient schedules. Experiments on Transformer workloads show that FFM’s runtime scales roughly linearly with the number of computation steps, achieving speedups of over 1,000× compared to existing state‑of‑the‑art mappers. The work appears in the arXiv preprint arXiv:2602.15166 (Feb 2026).

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