• Custom IC design has demanding technical requirements to produce accurate simulation results for timing and power analysis in the shortest run times. • EDA vendors have been rushing to use AI and ML technology to meet these analysis requirements. • I attended a webinar from Siemens on accelerating iterative design cycles with Solido additive learning techniques to understand their approach to benefit custom IC designers. • Mohamed Atousa, Product Management Manager at Siemens started with an overview of their custom IC platform with tools spanning from schematic capture, variation-aware design, physical layout, library characterization, IP QA, and SPICE simulation to generative and agentic AI. • Within the Solido Design Environment are multiple analysis tools and the focus of this webinar was on the additive learning features used inPVTMC Verifierand theHigh-Sigma Verifiertools to achieve a 3X to 20X speed-up on incremental and iterative runs. • High-quality IC designs require variation-aware verification flows, yet the traditional Monte Carlo simulation methods run too slowly, but using extrapolation techniques cannot find outliers or model non-Gaussian behavior, and most simulation jobs are iterative.
Article Summaries:
- Siemens showcased its Solido platform at a webinar, highlighting additive learning techniques that accelerate custom IC design cycles. The new AI‑driven tools-PVTMC Verifier and High‑Sigma Verifier-offer 3×‑20× speed‑ups for incremental runs, achieving 2×‑10× faster Monte‑Carlo verification and 1,000X‑1,000,000X faster 6‑sigma yield checks while preserving SPICE accuracy. Additive learning reuses AI models from prior jobs, reducing re‑verification time after PDK or design changes. Microchip’s pilot reported a 3.7× reduction in simulations and a 4.1× wall‑clock speed‑up on bandgap reference circuits, cutting iteration time from 20‑30 days to a few hours.
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