Compiler

LLVM Clang 22 Compiler Performance Largely Unchanged Over Clang 21 On AMD Zen 5

• LLVM Clang 22 Compiler Performance Largely Unchanged Over Clang 21 On AMD Zen 5 With yesterday’s stable release of the LLVM Clang 22 compiler it didn’t take long for Phoronix rea

LLVM/Clang 22 Compiler Officially Released With Many Improvements

• LLVM/Clang 22 Compiler Officially Released With Many Improvements LLVM/Clang 22.1 was released overnight as the first stable release of the LLVM 22 series. • This is a nice, feat

tiny-gpu-compiler: An educational MLIR-based compiler targeting open-source GPU hardware

• Tiny-gpu-compiler: An educational MLIR-based compiler targeting open-source GPU hardware I built an open-source compiler that uses MLIR to compile a C-like GPU kernellanguage dow

depyf: Open the Opaque Box of PyTorch Compiler for Machine Learning Researchers

• depyf: Open the Opaque Box of PyTorch Compiler for Machine Learning Researchers depyf: Open the Opaque Box of PyTorch Compiler for Machine Learning Researchers AuthorsKaichao You

🗓️ WiCT Meetup - Saturday, March 14, 2026: Compiler Optimizations for CPU-GPU Heterogeneous Systems

• 🗓️ WiCT Meetup - Saturday, March 14, 2026: Compiler Optimizations for CPU-GPU Heterogeneous Systems WiCT Meetup - Saturday, March 14, 2026: Compiler Optimizations for CPU-GPU Het

AMD AOMP 23.0-0 Compiler Continues Enhancing Fortran Support

• AMD AOMP 23.0-0 Compiler Continues Enhancing Fortran Support AMD AOMP 23.0-0 was released overnight as the latest build of this LLVM/Clang downstream that continues to carry the

[SCEV] question about inferring nsw flags

• SCEV struggles to infer nsw flags for AddRec subscripts in conditional stores. • Example loop uses i to index array with conditions. • Current SCEV cannot deduce overflow behavio

Where to start fixing an opt-pass for MIPS1

• MIPS1 load delay slots ignored when load occurs in branch delay slot. • Issue originates in CodeGen Prepareopt pass during optimization of MIPS1 code. • Developer seeks to fix ra

Side effects and mayLoad/mayStore in MachineIR

• MachineScheduler blocks reordering of side-effecting instructions with loads/stores via a barrier chain. • MachineSink can still sink a ds_load across a workgroup fence, raising

Establishing a Scalable Sparse Ecosystem with the Universal Sparse Tensor

• UST decouples tensor sparsity from memory representation, enabling flexible storage formats. • Developers describe storage via a DSL, focusing solely on sparsity patterns. • Comp

Taming 2,500 compiler warnings with CodeQL, an OpenVPN2 case study

• Taming 2,500 compiler warnings with CodeQL, an OpenVPN2 case study Why are implicit integer conversions a problem in C? • During our security review of OpenVPN2, we faced a daunt