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    <title>Compiler on Tenu Tech Brief</title>
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    <description>Recent content in Compiler on Tenu Tech Brief</description>
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      <title>LLVM Clang 22 Compiler Performance Largely Unchanged Over Clang 21 On AMD Zen 5</title>
      <link>https://cluster-site.onrender.com/posts/llvm-clang-22-compiler-performance-largely-unchanged-over-clang-21-on-amd-zen-5/</link>
      <pubDate>Wed, 25 Feb 2026 20:05:00 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/llvm-clang-22-compiler-performance-largely-unchanged-over-clang-21-on-amd-zen-5/</guid>
      <description>• LLVM Clang 22 Compiler Performance Largely Unchanged Over Clang 21 On AMD Zen 5 With yesterday&amp;rsquo;s stable release of the LLVM Clang 22 compiler it didn&amp;rsquo;t take long for Phoronix rea</description>
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      <title>LLVM/Clang 22 Compiler Officially Released With Many Improvements</title>
      <link>https://cluster-site.onrender.com/posts/llvm/clang-22-compiler-officially-released-with-many-improvements/</link>
      <pubDate>Tue, 24 Feb 2026 11:13:20 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/llvm/clang-22-compiler-officially-released-with-many-improvements/</guid>
      <description>• LLVM/Clang 22 Compiler Officially Released With Many Improvements LLVM/Clang 22.1 was released overnight as the first stable release of the LLVM 22 series. • This is a nice, feat</description>
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    <item>
      <title>tiny-gpu-compiler: An educational MLIR-based compiler targeting open-source GPU hardware</title>
      <link>https://cluster-site.onrender.com/posts/tiny-gpu-compiler-an-educational-mlir-based-compiler-targeting-open-source-gpu-hardware/</link>
      <pubDate>Tue, 24 Feb 2026 06:01:49 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/tiny-gpu-compiler-an-educational-mlir-based-compiler-targeting-open-source-gpu-hardware/</guid>
      <description>• Tiny-gpu-compiler: An educational MLIR-based compiler targeting open-source GPU hardware I built an open-source compiler that uses MLIR to compile a C-like GPU kernellanguage dow</description>
    </item>
    <item>
      <title>depyf: Open the Opaque Box of PyTorch Compiler for Machine Learning Researchers</title>
      <link>https://cluster-site.onrender.com/posts/depyf-open-the-opaque-box-of-pytorch-compiler-for-machine-learning-researchers/</link>
      <pubDate>Tue, 24 Feb 2026 00:00:00 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/depyf-open-the-opaque-box-of-pytorch-compiler-for-machine-learning-researchers/</guid>
      <description>• depyf: Open the Opaque Box of PyTorch Compiler for Machine Learning Researchers depyf: Open the Opaque Box of PyTorch Compiler for Machine Learning Researchers AuthorsKaichao You</description>
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    <item>
      <title>🗓️ WiCT Meetup - Saturday, March 14, 2026: Compiler Optimizations for CPU-GPU Heterogeneous Systems</title>
      <link>https://cluster-site.onrender.com/posts/%EF%B8%8F-wict-meetup-saturday-march-14-2026-compiler-optimizations-for-cpu-gpu-heterogeneous-systems/</link>
      <pubDate>Mon, 23 Feb 2026 18:06:47 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/%EF%B8%8F-wict-meetup-saturday-march-14-2026-compiler-optimizations-for-cpu-gpu-heterogeneous-systems/</guid>
      <description>• 🗓️ WiCT Meetup - Saturday, March 14, 2026: Compiler Optimizations for CPU-GPU Heterogeneous Systems WiCT Meetup - Saturday, March 14, 2026: Compiler Optimizations for CPU-GPU Het</description>
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    <item>
      <title>AMD AOMP 23.0-0 Compiler Continues Enhancing Fortran Support</title>
      <link>https://cluster-site.onrender.com/posts/amd-aomp-23.0-0-compiler-continues-enhancing-fortran-support/</link>
      <pubDate>Sat, 21 Feb 2026 10:55:13 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/amd-aomp-23.0-0-compiler-continues-enhancing-fortran-support/</guid>
      <description>• AMD AOMP 23.0-0 Compiler Continues Enhancing Fortran Support AMD AOMP 23.0-0 was released overnight as the latest build of this LLVM/Clang downstream that continues to carry the</description>
    </item>
    <item>
      <title>[SCEV] question about inferring nsw flags</title>
      <link>https://cluster-site.onrender.com/posts/scev-question-about-inferring-nsw-flags/</link>
      <pubDate>Tue, 17 Feb 2026 21:13:29 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/scev-question-about-inferring-nsw-flags/</guid>
      <description>• SCEV struggles to infer nsw flags for AddRec subscripts in conditional stores. • Example loop uses i to index array with conditions. • Current SCEV cannot deduce overflow behavio</description>
    </item>
    <item>
      <title>Where to start fixing an opt-pass for MIPS1</title>
      <link>https://cluster-site.onrender.com/posts/where-to-start-fixing-an-opt-pass-for-mips1/</link>
      <pubDate>Tue, 17 Feb 2026 20:23:45 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/where-to-start-fixing-an-opt-pass-for-mips1/</guid>
      <description>• MIPS1 load delay slots ignored when load occurs in branch delay slot. • Issue originates in CodeGen Prepareopt pass during optimization of MIPS1 code. • Developer seeks to fix ra</description>
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    <item>
      <title>Side effects and mayLoad/mayStore in MachineIR</title>
      <link>https://cluster-site.onrender.com/posts/side-effects-and-mayload/maystore-in-machineir/</link>
      <pubDate>Tue, 17 Feb 2026 17:47:47 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/side-effects-and-mayload/maystore-in-machineir/</guid>
      <description>• MachineScheduler blocks reordering of side-effecting instructions with loads/stores via a barrier chain. • MachineSink can still sink a ds_load across a workgroup fence, raising</description>
    </item>
    <item>
      <title>Establishing a Scalable Sparse Ecosystem with the Universal Sparse Tensor</title>
      <link>https://cluster-site.onrender.com/posts/establishing-a-scalable-sparse-ecosystem-with-the-universal-sparse-tensor/</link>
      <pubDate>Fri, 30 Jan 2026 18:00:00 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/establishing-a-scalable-sparse-ecosystem-with-the-universal-sparse-tensor/</guid>
      <description>• UST decouples tensor sparsity from memory representation, enabling flexible storage formats. • Developers describe storage via a DSL, focusing solely on sparsity patterns. • Comp</description>
    </item>
    <item>
      <title>Taming 2,500 compiler warnings with CodeQL, an OpenVPN2 case study</title>
      <link>https://cluster-site.onrender.com/posts/taming-2500-compiler-warnings-with-codeql-an-openvpn2-case-study/</link>
      <pubDate>Thu, 25 Sep 2025 11:00:00 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/taming-2500-compiler-warnings-with-codeql-an-openvpn2-case-study/</guid>
      <description>• Taming 2,500 compiler warnings with CodeQL, an OpenVPN2 case study Why are implicit integer conversions a problem in C? • During our security review of OpenVPN2, we faced a daunt</description>
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