Where to start fixing an opt-pass for MIPS1

• MIPS1 load delay slots ignored when load occurs in branch delay slot. • Issue originates in CodeGen Prepareopt pass during optimization of MIPS1 code. • Developer seeks to fix rarely-used MIPS1 target with limited time and experience. • Key LLVM passes to examine: MipsBranchExpansion, MipsDelaySlotFiller, and bundle handling. • Use -print-after-all to view branch and load delay slot representation. • Issue tracked in LLVM issue tracker; collaboration with Cody provides deeper insights.

Article Summaries:

• Hello LLVM-Experts, working on a personal Rust project for the PlayStation 1, we noticed that a specific setup can generate code that is not correct for the MIPS1 target. Together with Cody we had a deep dive into what exactly happens. To cut a long story short, we found out that MIPS1 load delay slots are not respected when the load is happening in a branch delay slot. Further we identified that the issue is setup during the CodeGen Prepare opt pass. However we do not know enough about this optimization pass nor any optimization pass to know where exactly to start… We know that MIPS1 is not a

Sources:

• https://discourse.llvm.org/t/where-to-start-fixing-an-opt-pass-for-mips1/89857