• Navitas Semiconductor has announced its 5th-generation GeneSiC platform featuring high-voltage trench-assisted planar (TAP) SiC MOSFETs, describing it as a significant advancement over previous generations. • The new 1200-V MOSFET line complements Navitas’ ultra-high-voltage 2.3-kV and 3.3-kV devices based on its 4th-generation GeneSiC technology. • The latest generation incorporates the company’s most compact TAP architecture to date, combining planar-gate ruggedness with trench-enabled performance gains to improve efficiency and long-term reliability. • It targets high-voltage applications including AI data centers, grid and energy infrastructure, and industrial electrification. • Compared with the prior 1200-V devices, the new generation delivers a 35% improvement in R DS(on) × Q GD figure of merit, reducing switching losses and enabling cooler, higher-frequency operation. • About a 25% improvement in Q GD /Q GS ratio, together with a stable high threshold voltage (V GS,TH ≥ 3 V), strengthens switching robustness and improves immunity to parasitic turn-on in high-noise environments.
Article Summaries:
- Navitas Semiconductor unveiled its 5th‑generation GeneSiC platform, featuring high‑voltage trench‑assisted planar (TAP) SiC MOSFETs. The new 1200‑V line builds on the company’s 4th‑generation GeneSiC, which already powers 2.3‑kV and 3.3‑kV devices. The compact TAP architecture merges planar‑gate durability with trench‑enabled performance, delivering a 35 % improvement in the RDS(on) × QGD figure of merit and a 25 % boost in the QGD/QGS ratio. These gains reduce switching losses, enable cooler, higher‑frequency operation, and enhance robustness in noisy environments. Navitas plans to launch products based on this technology in the coming months, targeting AI data centers, grid and energy infrastructure, and industrial electrification.
Sources: