Architectures

Optimizing Allreduce Operations for Modern Heterogeneous Architectures with Multiple Processes per GPU

• Computer Science > Distributed, Parallel, and Cluster Computing [Submitted on 18 Aug 2025 (v1), last revised 24 Feb 2026 (this version, v2)] Title:Optimizing Allreduce Operations

Integrating eFPGA for Hybrid Signal Processing Architectures

• Fixed logic or software • eFPGA offers a smarter middle ground-enabling reconfigurable, ASIC-class signal processing without the re-spin • Here’s how to architect it • The post I

Security boundaries in agentic architectures

• 8 min read Most agents today run generated code with full access to your secrets. • As more agents adopt coding agent patterns, where they read filesystems, run shell commands, a

AI is stress-testing processor architectures and RISC-V fits the moment

• Every major computing era has been defined not by technology, but by a dominant workload-and by how well processor architectures adapted to it. • The personal computer era reward

Support RAJA and Scientific Applications on RVV Architectures

• Project Snapshot In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. • RAJA is a C++ li

Asynchronous Verified Semantic Caching for Tiered LLM Architectures

• Asynchronous Verified Semantic Caching for Tiered LLM Architectures Asynchronous Verified Semantic Caching for Tiered LLM Architectures AuthorsAsmit Kumar Singh, Haozhe Wang, Lax