Architectures on Tenu Tech Brief https://cluster-site.onrender.com/tags/architectures/ Recent content in Architectures on Tenu Tech Brief Hugo -- 0.146.0 en-us Thu, 26 Feb 2026 06:03:06 +0000 Optimizing Allreduce Operations for Modern Heterogeneous Architectures with Multiple Processes per GPU https://cluster-site.onrender.com/posts/optimizing-allreduce-operations-for-modern-heterogeneous-architectures-with-multiple-processes-per-gpu/ Thu, 26 Feb 2026 05:00:00 +0000 https://cluster-site.onrender.com/posts/optimizing-allreduce-operations-for-modern-heterogeneous-architectures-with-multiple-processes-per-gpu/ • Computer Science > Distributed, Parallel, and Cluster Computing [Submitted on 18 Aug 2025 (v1), last revised 24 Feb 2026 (this version, v2)] Title:Optimizing Allreduce Operations Integrating eFPGA for Hybrid Signal Processing Architectures https://cluster-site.onrender.com/posts/integrating-efpga-for-hybrid-signal-processing-architectures/ Wed, 25 Feb 2026 14:00:00 +0000 https://cluster-site.onrender.com/posts/integrating-efpga-for-hybrid-signal-processing-architectures/ • Fixed logic or software • eFPGA offers a smarter middle ground-enabling reconfigurable, ASIC-class signal processing without the re-spin • Here’s how to architect it • The post I Security boundaries in agentic architectures https://cluster-site.onrender.com/posts/security-boundaries-in-agentic-architectures/ Wed, 25 Feb 2026 06:41:52 +0000 https://cluster-site.onrender.com/posts/security-boundaries-in-agentic-architectures/ • 8 min read Most agents today run generated code with full access to your secrets. • As more agents adopt coding agent patterns, where they read filesystems, run shell commands, a AI is stress-testing processor architectures and RISC-V fits the moment https://cluster-site.onrender.com/posts/ai-is-stress-testing-processor-architectures-and-risc-v-fits-the-moment/ Thu, 19 Feb 2026 07:17:49 +0000 https://cluster-site.onrender.com/posts/ai-is-stress-testing-processor-architectures-and-risc-v-fits-the-moment/ • Every major computing era has been defined not by technology, but by a dominant workload-and by how well processor architectures adapted to it. • The personal computer era reward Support RAJA and Scientific Applications on RVV Architectures https://cluster-site.onrender.com/posts/support-raja-and-scientific-applications-on-rvv-architectures/ Tue, 17 Feb 2026 09:09:50 +0000 https://cluster-site.onrender.com/posts/support-raja-and-scientific-applications-on-rvv-architectures/ • Project Snapshot In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. • RAJA is a C++ li Asynchronous Verified Semantic Caching for Tiered LLM Architectures https://cluster-site.onrender.com/posts/asynchronous-verified-semantic-caching-for-tiered-llm-architectures/ Mon, 16 Feb 2026 00:00:00 +0000 https://cluster-site.onrender.com/posts/asynchronous-verified-semantic-caching-for-tiered-llm-architectures/ • Asynchronous Verified Semantic Caching for Tiered LLM Architectures Asynchronous Verified Semantic Caching for Tiered LLM Architectures AuthorsAsmit Kumar Singh, Haozhe Wang, Lax