• jurahul 1 GPU targets generally have to define vector registers to address N consecutive scalar registers for use in vector instructions. • These are usually defined using RegisterTuples in the target register file description, and TableGen synthesizes these vector register by concatenating the names of their scalar components (for example, X0_X1_X2_X3 ). • Similarly, sub-register indices that are synthesized by concatenating other subreg indices are named with concatenation of components (sub0_sub1_sub2_sub3 ). • When we have vector registers with > 8 components, these register names become too long. • For some targets with > 256 wide vectors, these names are just too big to read. • Would it make sense to have a mode in TableGen to generate more compact names for these common cases.
Article Summaries:
- A proposal to add a “CompactRegisterNames” option in LLVM’s TableGen has been discussed, aiming to shorten long vector and sub‑register names that arise from concatenating many scalar components (e.g., X0_X1_X2_X3). The suggested syntax replaces contiguous ranges with a compact form such as X0__X3 or, alternatively, X0_TO_3, optionally including stride information. The feature would be opt‑in, improving readability of MIR dumps and reducing generated .inc file size. NVIDIA has expressed interest in adopting the change for its downstream targets, while attempts to apply it to AMDGPU hit static‑assert issues. Two pull requests (by jurahul and nvjle) provide proof‑of‑concept implementations.
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