• Cortex‑A520, Arm’s next‑gen efficient core, follows A510 with enhanced power efficiency and microarchitecture. • Codename “Hayes,” it targets lowest area and cost‑constrained devices with ARMv9.2 ISA support. • QARMA3 address‑authentication reduces PAC overhead to <1% and cuts latency, boosting security efficiency. • Branch prediction and data prefetching improvements deliver better performance‑efficiency than pipeline changes. • Removed or scaled‑down ALU and other features to reallocate power to critical areas. • Designed to pair with Cortex‑A720 via DSU‑120, enabling flexible big‑little core configurations.

Article Summaries:

  • Arm unveiled the Cortex‑A520, a successor to the Cortex‑A510, as part of its Client Tech Day lineup. The new core targets ultra‑low power and small area for cost‑constrained devices, updating its ISA to Armv9.2 and adding PAC support via the QARMA3 algorithm, which cuts PAC overhead to under 1 %. Microarchitectural tweaks focus on branch prediction and data prefetching, while a removed ALU reduces pipeline power consumption. Arm reports the A520 can deliver 22 % lower power at similar performance or 8 % higher performance at the same power level, and is designed to pair with the new Cortex‑A720 using the DSU‑120.

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