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    <title>Llvm on Tenu Tech Brief</title>
    <link>https://cluster-site.onrender.com/tags/llvm/</link>
    <description>Recent content in Llvm on Tenu Tech Brief</description>
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      <title>CANCELLED RISC-V LLVM sync-up call February 26th 2026</title>
      <link>https://cluster-site.onrender.com/posts/cancelled-risc-v-llvm-sync-up-call-february-26th-2026/</link>
      <pubDate>Wed, 25 Feb 2026 20:39:31 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/cancelled-risc-v-llvm-sync-up-call-february-26th-2026/</guid>
      <description>• LLVM Discussion Forums CANCELLED RISC-V LLVM sync-up call February 26th 2026 Code Generation RISCV asb February 25, 2026, 8:39pm 1 We&amp;rsquo;ll skip tomorrow&amp;rsquo;s meeting due to lack of ag</description>
    </item>
    <item>
      <title>LLVM Clang 22 Compiler Performance Largely Unchanged Over Clang 21 On AMD Zen 5</title>
      <link>https://cluster-site.onrender.com/posts/llvm-clang-22-compiler-performance-largely-unchanged-over-clang-21-on-amd-zen-5/</link>
      <pubDate>Wed, 25 Feb 2026 20:05:00 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/llvm-clang-22-compiler-performance-largely-unchanged-over-clang-21-on-amd-zen-5/</guid>
      <description>• LLVM Clang 22 Compiler Performance Largely Unchanged Over Clang 21 On AMD Zen 5 With yesterday&amp;rsquo;s stable release of the LLVM Clang 22 compiler it didn&amp;rsquo;t take long for Phoronix rea</description>
    </item>
    <item>
      <title>Getting started with understanding LLVM internals</title>
      <link>https://cluster-site.onrender.com/posts/getting-started-with-understanding-llvm-internals/</link>
      <pubDate>Tue, 24 Feb 2026 21:41:45 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/getting-started-with-understanding-llvm-internals/</guid>
      <description>• Getting started with understanding LLVM internals Hello everyone, I am currently studying LLVM and would appreciate guidance on how to build a structured understanding of its int</description>
    </item>
    <item>
      <title>AMD&#39;s HIP Moves To Using LLVM&#39;s New Offload Driver By Default</title>
      <link>https://cluster-site.onrender.com/posts/amds-hip-moves-to-using-llvms-new-offload-driver-by-default/</link>
      <pubDate>Tue, 24 Feb 2026 13:09:31 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/amds-hip-moves-to-using-llvms-new-offload-driver-by-default/</guid>
      <description>• AMD&amp;rsquo;s HIP Moves To Using LLVM&amp;rsquo;s New Offload Driver By Default A change merged to upstream LLVM Git yesterday for LLVM 23 is moving AMD&amp;rsquo;s HIP to using the new/modern offload drive</description>
    </item>
    <item>
      <title>Black Formatter Version 23.x Faces CVE-2024-21503</title>
      <link>https://cluster-site.onrender.com/posts/black-formatter-version-23.x-faces-cve-2024-21503/</link>
      <pubDate>Tue, 24 Feb 2026 12:39:42 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/black-formatter-version-23.x-faces-cve-2024-21503/</guid>
      <description>• LLVM recommends using Black 23.x for Python code formatting. • Black 23.x faces CVE-2024-21503, a regex denial-of-service vulnerability. • The vulnerability could trigger excessi</description>
    </item>
    <item>
      <title>LLVM/Clang 22 Compiler Officially Released With Many Improvements</title>
      <link>https://cluster-site.onrender.com/posts/llvm/clang-22-compiler-officially-released-with-many-improvements/</link>
      <pubDate>Tue, 24 Feb 2026 11:13:20 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/llvm/clang-22-compiler-officially-released-with-many-improvements/</guid>
      <description>• LLVM/Clang 22 Compiler Officially Released With Many Improvements LLVM/Clang 22.1 was released overnight as the first stable release of the LLVM 22 series. • This is a nice, feat</description>
    </item>
    <item>
      <title>TVM &#43; LLVM flow for custom NPU: Where should the Conv2d tiling and memory management logic reside?</title>
      <link>https://cluster-site.onrender.com/posts/tvm--llvm-flow-for-custom-npu-where-should-the-conv2d-tiling-and-memory-management-logic-reside/</link>
      <pubDate>Tue, 24 Feb 2026 10:48:23 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/tvm--llvm-flow-for-custom-npu-where-should-the-conv2d-tiling-and-memory-management-logic-reside/</guid>
      <description>• Hi everyone, I&amp;rsquo;m a junior compiler engineer recently working on a backend for a custom NPU. • I&amp;rsquo;m looking for some architectural advice regarding the split of responsibilities be</description>
    </item>
    <item>
      <title>LLVM 22.1.0 Released!</title>
      <link>https://cluster-site.onrender.com/posts/llvm-22.1.0-released/</link>
      <pubDate>Tue, 24 Feb 2026 09:03:10 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/llvm-22.1.0-released/</guid>
      <description>• LLVM 22.1.0 Released! • We are happy to announce that LLVM 22.1.0 is now released! • This includes the main LLVM project, and its subprojects including clang, lld, libc++, and ML</description>
    </item>
    <item>
      <title>LLVM Weekly - #634, February 23rd 2026</title>
      <link>https://cluster-site.onrender.com/posts/llvm-weekly-%23634-february-23rd-2026/</link>
      <pubDate>Mon, 23 Feb 2026 20:37:02 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/llvm-weekly-%23634-february-23rd-2026/</guid>
      <description>• LLVM Weekly - #634, February 23rd 2026 LLVM Weekly -#634, February 23rd 2026 If you prefer, you can read the canonical version of this issue athttps://llvmweekly.org/issue/634. •</description>
    </item>
    <item>
      <title>LLVM Embedded Toolchains Working Group call this Thursday, Feb 26</title>
      <link>https://cluster-site.onrender.com/posts/llvm-embedded-toolchains-working-group-call-this-thursday-feb-26/</link>
      <pubDate>Mon, 23 Feb 2026 15:30:06 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/llvm-embedded-toolchains-working-group-call-this-thursday-feb-26/</guid>
      <description>• LLVM Embedded Toolchains Working Group call this Thursday, Feb 26 Hello, This is to confirm theLLVM Embedded Toolchains Working Group sync upthis week. • Agenda: Reviews and RFCs</description>
    </item>
    <item>
      <title>[RFC] Enforce Rule of Three</title>
      <link>https://cluster-site.onrender.com/posts/rfc-enforce-rule-of-three/</link>
      <pubDate>Wed, 18 Feb 2026 21:01:00 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/rfc-enforce-rule-of-three/</guid>
      <description>• LLVM has many RAII classes that define destructors but omit copy constructors/assignments. • Implicit copying can cause double deletes, state corruption, and subtle bugs. • The R</description>
    </item>
    <item>
      <title>[SCEV] question about inferring nsw flags</title>
      <link>https://cluster-site.onrender.com/posts/scev-question-about-inferring-nsw-flags/</link>
      <pubDate>Tue, 17 Feb 2026 21:13:29 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/scev-question-about-inferring-nsw-flags/</guid>
      <description>• SCEV struggles to infer nsw flags for AddRec subscripts in conditional stores. • Example loop uses i to index array with conditions. • Current SCEV cannot deduce overflow behavio</description>
    </item>
    <item>
      <title>Where to start fixing an opt-pass for MIPS1</title>
      <link>https://cluster-site.onrender.com/posts/where-to-start-fixing-an-opt-pass-for-mips1/</link>
      <pubDate>Tue, 17 Feb 2026 20:23:45 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/where-to-start-fixing-an-opt-pass-for-mips1/</guid>
      <description>• MIPS1 load delay slots ignored when load occurs in branch delay slot. • Issue originates in CodeGen Prepareopt pass during optimization of MIPS1 code. • Developer seeks to fix ra</description>
    </item>
    <item>
      <title>Sphinx documentation stopped updating</title>
      <link>https://cluster-site.onrender.com/posts/sphinx-documentation-stopped-updating/</link>
      <pubDate>Tue, 17 Feb 2026 19:19:02 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/sphinx-documentation-stopped-updating/</guid>
      <description>• Sphinx documentation build halted, no updates visible for weeks. • Recent clang‑tidy docs changes (~2 weeks) not reflected in the public repository. • publish‑*-docs CI jobs unre</description>
    </item>
    <item>
      <title>[Modules] Bi-Weekly Meetup Notes, Feb 17, 2026</title>
      <link>https://cluster-site.onrender.com/posts/modules-bi-weekly-meetup-notes-feb-17-2026/</link>
      <pubDate>Tue, 17 Feb 2026 17:52:45 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/modules-bi-weekly-meetup-notes-feb-17-2026/</guid>
      <description>• Michael highlights ongoing cleanup of implicit module mechanism, aiming to remove unnecessary components. • Naveen landed patch untangling dependency scanning; Ben proposes adopt</description>
    </item>
    <item>
      <title>Side effects and mayLoad/mayStore in MachineIR</title>
      <link>https://cluster-site.onrender.com/posts/side-effects-and-mayload/maystore-in-machineir/</link>
      <pubDate>Tue, 17 Feb 2026 17:47:47 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/side-effects-and-mayload/maystore-in-machineir/</guid>
      <description>• MachineScheduler blocks reordering of side-effecting instructions with loads/stores via a barrier chain. • MachineSink can still sink a ds_load across a workgroup fence, raising</description>
    </item>
    <item>
      <title>LLVM Weekly - #633, February 16th 2026</title>
      <link>https://cluster-site.onrender.com/posts/llvm-weekly-%23633-february-16th-2026/</link>
      <pubDate>Mon, 16 Feb 2026 21:11:22 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/llvm-weekly-%23633-february-16th-2026/</guid>
      <description>• LLVM Weekly - #633, February 16th 2026 LLVM Weekly -#633, February 16th 2026 If you prefer, you can read the canonical version of this issue athttps://llvmweekly.org/issue/633. •</description>
    </item>
    <item>
      <title>Introducing constant-time support for LLVM to protect cryptographic code</title>
      <link>https://cluster-site.onrender.com/posts/introducing-constant-time-support-for-llvm-to-protect-cryptographic-code/</link>
      <pubDate>Tue, 02 Dec 2025 12:00:00 +0000</pubDate>
      <guid>https://cluster-site.onrender.com/posts/introducing-constant-time-support-for-llvm-to-protect-cryptographic-code/</guid>
      <description>• Introducing constant-time support for LLVM to protect cryptographic code Trail of Bits has developed constant-time coding support for LLVM, providing developers with compiler-lev</description>
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