• SEALSQ Corp(NASDAQ: LAES) andLattice Semiconductor(NASDAQ: LSCC) have announced a collaboration to integrate advanced post-quantum cryptography (PQC) into select Lattice FPGA solutions using a unified TPM-FPGA architecture. • This collaboration addresses the urgent requirement for quantum-resistant security in mission-critical edge computing and industrial infrastructure. • By combining SEALSQ’s specialized post-quantum hardware with Lattice’s low-power, secure FPGA platforms, the partnership provides a scalable reference design for organizations transitioning toCNSA 2.0andNISTstandards. • The joint solution features a Proof-of-Concept (PoC) that integrates a Lattice secure FPGA with SEALSQ’sQS7001andQVault TPMsecure Root-of-Trust (RoT). • The QS7001 is a hardware-embedded PQC chip designed on a 32-bit secured RISC-V architecture. • It provides hardware acceleration for NIST-selected algorithms, including ML-KEM (formerly Kyber) for key encapsulation and ML-DSA (formerly Dilithium) for digital signatures.
Article Summaries:
- SEALSQ Corp and Lattice Semiconductor announced a partnership to embed post‑quantum cryptography (PQC) into Lattice FPGA products via a unified TPM‑FPGA architecture. The collaboration combines SEALSQ’s QS7001 PQC chip and QVault TPM with Lattice’s low‑power, secure FPGAs, delivering a reference design that supports NIST‑selected algorithms such as ML‑KEM and ML‑DSA. Key features include a quantum‑resistant root‑of‑trust, in‑field crypto‑agility, up to 10× performance gains from silicon‑based acceleration, and design readiness for Common Criteria EAL5+ and FIPS 140‑3. The solution will be demoed at Embedded World 2026 in Nuremberg as part of the Year of Quantum Security 2026 initiative.
Sources: