• Integrates HBM4 memory with chiplet architecture for ultra‑high bandwidth router cores. • Employs in‑package optics to replace copper interconnects, cutting latency and power. • Demonstrates 10‑fold throughput increase while halving energy per bit compared to legacy designs. • Enables modular scaling, allowing future upgrades without redesigning entire router stack. • Validated through silicon prototypes from Technion, UC Berkeley, and UC San Diego.
Article Summaries:
- A new technical paper “Scaling Routers with In-Package Optics and High-Bandwidth Memories” was posted by researchers at Technion, UC Berkeley and UC San Diego. Abstract “This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optics. We propose a novel internet router architecture that employs these technologies to achieve a petabit/sec router within a single integrated package. At the top-level, we introduce a novel split-parallel sw
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