• An interesting detail about the Intel 8087 floating point processor (FPU) is that it’s a co-processor that shares a bus with the 8086 or 8088 CPU and system memory, which means that somehow both the CPU and FPU need to know which instructions are intended for the FPU. • Key to this are eight so-calledESCAPEopcodes that are assigned to the co-processor, as explainedin a recent articleby [Ken Shirriff]. • The 8087 thus waits to see whether it sees these opcodes, but since it doesn’t have access to the CPU’s registers, sharing data has to occur via system memory. • The address for this is calculated by the CPU and read from by the CPU, with this address registered by the FPU and stores for later use in its BIU register. • From there the instruction can be fully decoded and executed. • This decoding is mostly done by the microcode engine, withconditional instructionslikecosfeaturing circuitry that sprawls all over the IC.
Article Summaries:
- The Intel 8087 floating‑point unit (FPU) operates as a co‑processor on the same bus as the 8086/8088 CPU and system memory, requiring a mechanism to identify FPU‑specific instructions. Eight ESCAPE opcodes are reserved for the FPU; the CPU signals these, and the FPU, lacking direct register access, retrieves operands from memory using addresses calculated by the CPU. The FPU’s microcode engine decodes and executes these instructions, with only a few operations implemented directly in hardware at the bus interface. Due to limited ROM size (≈2 kB), the 8087 uses 22 microcode entry points, combining logic gates and PLAs to manage complex instruction sets efficiently.
Sources: